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EPA-Patente auf Speicherverwaltungsarithmetik



Ich frage mich, gegen wie viele der folgenden Patente die
Speicherverwaltung in Betriebssystemen wie Linux und FreeBSD verstoesst
und in wie weit man noch Speicher verwalten kann, ohne an diese (soweit
ich sehen kann) laecherlich trivialen und gruselig breiten Patente zu
stossen.

Ich liste hier mal nur ca 1/3 der EPA-Patente auf, die im Titel das
Stichwort Cache enthalten, und erklaere unten kurz das erste von diesen.

EP0359815 CACHE WITH AT LEAST TWO FILL SIZES
EP0232526 Virtual cache system using page level number generating CAM to
          access other memories for processing requests 
EP0541319 Write through virtual cache memory, alias addressing, and cache flushes
EP0348495 Method and apparatus using a cache and main memory for both
vector processing and scalar processing by prefetching cache blocks including vector data elements
EP0543991 IMPROVING COMPUTER PERFORMANCE BY SIMULATED
   CACHE ASSOCIATIVITY -- DIGITAL EQUIPMENT CORP (US)
EP0441508 Data storage using a cache. -- IBM (US)
EP0387247 Fast packetized data delivery for digital
   interactive television and video on demand. -- FIRSTPERSON INC (US)
EP0332908 Cache memory having pseudo virtual
   addressing. -- BULL HN INFORMATION SYST (IT)
EP0442474 Apparatus and method for controlling cache
   memory -- SANYO ELECTRIC CO (JP)
EP0471434 Methods and apparatus for controlling a
   multi-segment cache memory. -- SEAGATE TECHNOLOGY (KY)
EP0321793 Apparatus for forcing a reload from main
   memory upon cache memory error. -- HONEYWELL BULL (US)
EP0604009 Computer operation of video camera. -- IBM
EP0365117 Data-processing apparatus including a cache memory. -- INT COMPUTERS LTD (GB)
  instructions having natural concurrencies -- MCC DEV LTD (US)
EP0170525 Cache hierarchy design for use in a memory management unit
EP0320099 Multi-cache data storage system. -- INT COMPUTERS LTD (GB)
EP0349757 APPARATUS AND METHOD FOR ENHANCED VIRTUAL TO REAL ADDRESS TRANSLATION FOR ACCESSING A CACHE MEMORY UNIT -- BULL HN
   INFORMATION SYST (US)
EP0642086 Virtual address to physical address translation cache that supports multiple page sizes.
EP0752660 Client-server computer system and method utilizing a local client disk drive as a data cache -- SUN
   MICROSYSTEMS INC (US)
EP0601334 Method for observing program flow in a
   processor having internal cache memory. -- MOTOROLA INC (US)
EP0643853 SYSTEM FOR ACCESSING DISTRIBUTED DATA CACHE
   CHANNEL AT EACH NETWORK NODE TO PASS REQUESTS AND DATA
EP0461926 Multilevel inclusion in multilevel cache
   hierarchies. -- COMPAQ COMPUTER CORP (US)
EP0449369 A data processing system provided with a
   performance enhancing instruction cache. -- KONINKL PHILIPS
   ELECTRONICS NV (NL)
EP0749242 Hybrid video-on-demand -- IBM (US)
EP0312785 Method and system of cache management in a
   file sharing system. -- IBM (US)
EP0271187 Split instruction and operand cache
   management. -- AMDAHL CORP (US)
EP0404369 A method for maintaining cache coherence in
   a multiprocessor computer system. -- HEWLETT PACKARD CO (US)
EP0498654 Cache memory processing instruction data and
   data processor including the same. -- FUJITSU LTD (JP)
EP0459232 Partially decoded instruction cache. -- NAT
   SEMICONDUCTOR CORP (US)
EP0470736 Cache memory system. -- NCR CO (US)
EP0413856 A decoding method and apparatus for decoding
EP0593968 Cache-based data compression/decompression
EP0231574 Cup chip having tag comparator and address
   translation unit on chip and connected to off-chip cache and main
   memories -- MIPS COMPUTER SYSTEMS INC (US)
EP0582370 Disk drive controller with a posted write
   cache memory. -- COMPAQ COMPUTER CORP (US)
EP0270896 Graphics terminal for personal computer
EP0457403 Multilevel instruction cache, method for
   using said cache, method for compiling instructions for said cache and
   micro computer system using such a cache. -- KONINKL PHILIPS
EP0449368 Method for compiling computer instructions
   for increasing cache efficiency. -- KONINKL PHILIPS ELECTRONICS NV
EP0568221 Methods and apparatus for implementing a
   pseudo-LRU cache memory replacement scheme with a locking feature. --
EP0176972 Multiprocessor shared pipeline cache memory
   with split cycle and concurrent utilization -- HONEYWELL INF SYSTEMS
EP0598535 Pending write-back controller for a cache
   controller coupled to a packet switched memory bus. -- XEROX CORP
EP0481716 Control system for controlling cache storage
   unit. -- FUJITSU LTD (JP)
EP0397994 Multiprocessor cache memory system. -- IBM
EP0380861 Improved data consistency between cache
   memories and the main memory in a multi-processor computer system. --
....


Die folgende Patentansprueche verbieten es, einen Fehler in der
Speicherbelegung schnell aufzuheben.  Bei dem Verfahren von DEC enthaelt
jeder Speicherblock ein Gueltigkeits-Bit.  Ist dieses bei einem
fehlerhaften Speicherblock ausgeschaltet, so wird sofort eine ganze
uebergeordnete Gruppe aus meist 4 Bloecken beschrieben.  Ist es
eingeschaltet, so wird nur der eine Block neu geschrieben, da man dann
davon ausgeht, dass die Vierergruppe richtig belegt ist und nur an der
einen Stelle ein Fehler aufgetreten ist.  

   Claims
   
   Claims: 1. A method of sending information to a cache in a
   computer, the method comprising the steps of:
   searching the cache for the requested information;
   generating a miss signal when the requested
   information is not found;
   examining a valid bit of a data block in said cache
   where requested information should be located, when
   said miss signal is generated;
   filling said cache with N data blocks during a
   specified time interval if the valid bit is not on,
   said N data blocks including a data block
   containing said requested information; and
   filling said cache with P data blocks at one time
   if the valid bit is on, where P is less than N,
   said P blocks including a data block containing
   said requested information.
   2. A method of filling a cache in a computer with
   information, the method comprising the steps of:
   searching the cache for the requested information;
   generating a miss signal when the requested
   information is not found;
   evaluating a valid bit of a data block in said
   cache where requested information should be
   located, when said requested information is not
   within said cache;
   filling said cache with N data blocks during a
   specified time interval if the valid bit is off,
   said N data blocks including a data block
   containing said requested information;
   comparing a process identification number of said
   data block where said requested information should
   be located with a process identification number of
   a process being run by said computer;
   filling said cache with said N data blocks during a
   specified time interval if said process
   identification numbers do not match; and
   filling said cache with P data blocks during a
   specified time interval if said process
   identification numbers match, where P is less than
   N, said P including a data block containing said
   requested information.
   3. A method of filling a cache with information in a
   computer with information, the method comprising
   the steps of
   searching a data block in said cache for requested
   information and generating a miss signal when said
   requested information is not found;
   storing a count of generated miss signals;
   evaluating a valid bit of said data block which was
   searched;
   filling said cache with N data blocks during a
   specified time interval if the valid bit is off,
   said N data blocks including a data block
   containing said requested information;
   filling said cache with said N data blocks during a
   specified time interval if said process
   identification numbers do not match;
   comparing said count to a first threshold number of
   misses;
   filling said cache with said N data blocks during a
   specified time interval if said count exceeds said
   first threshold; ;
   writing P data blocks to said cache during a
   specified time interval when: said count does not
   exceed said first threshold; and said valid bit is
   on; wherein P is less than N, and said P blocks
   include a data block containing said requested
   information; and
   decrementing said count each time the search for
   said data block does not produce a miss signal, and
   continuing filling said cache with said N data
   blocks during a specified time interval until said
   count is below a second threshold.
   4. The method of claim 3, wherein said decrementing
   step decrements said count to zero each time a
   search for said data block does not product a miss
   signal.
   5. The method of claims 1, 2 or 3 further comprising
   the steps of:
   storing a location of said miss when searching said
   cache results in said miss signal being generated;
   comparing said stored miss location with a location
   of a next occurring miss; and
   filling the cache with said N data blocks during a
   specified time interval if said stored miss
   location and said next occurring miss location are
   within a preset distance from one another.
   6. A method according to claim 5, wherein the present
   distance is a same aligned group of blocks.
   7. An apparatus for filling a cache of a computer with
   information, comprising:
   means for evaluating valid bits of a data block in
   said cache; and
   means for filling said cache with different sized
   blocks of data during a specified time interval in
   response to evaluation of said valid bit by said
   means for evaluating.
   8. The apparatus of claim 6, further comprising means
   for comparing a process identification number of
   said data block with a process identification
   number of a process being run by-said computer,
   wherein said means for filling fills said cache
   with different sized blocks in response to said
   comparison of said process identification numbers
   by said means for comparing.
   9. The apparatus of Claim 6, wherein said cache is a
   translation buffer.
   10. The method of Claims 1, 2 or 3, wherein N is 4 and
   P is 1.
   11. The method of claim 3, further comprising the step
   of comparing a process identification number of
   said data block which was searched with a process
   identification number of a process being run by
   said computer, and wherein said process
   identification numbers must match as a condition
   for the performance of P data blocks.
   12. The method of claims 1, 2 or 3 further comprising
   the steps of:
   storing a location of said miss when searching said
   cache results in said miss signal being generated;
   comparing said stored miss location with a location
   of a next occurring miss; and
   filling the cache with said N data blocks during a
   specified time interval if said stored miss
   location is a first block in an aligned group of
   blocks.
     _________________________________________________________________
   
   Data supplied from the esp@cenet database - l2